NodeLoop

1-Wire Protocol: A Guide to Timing and Waveforms

Precise microsecond timing is the key to a reliable 1-Wire implementation. This guide details the waveforms for every step of the process.

The 1-Wire protocol, developed by Dallas Semiconductor (now part of Maxim Integrated), enables communication with devices like the popular DS18B20 temperature sensor, EEPROMs, or iButton keys using only a single data line (DQ) and a ground reference.

The bus is open-drain, meaning devices can only pull the line low. A pull-up resistor (typically 4.7kΩ) is required to return the line to its idle high state when no device is transmitting. All communication is initiated by a master device (e.g., a microcontroller), and timing is critical.

Bus Reset & Presence Pulse

Every 1-Wire transaction must begin with a reset sequence. This sequence allows the master to detect if any slave devices are present on the bus. It consists of three parts:

  1. Master Reset Pulse: The master pulls the DQ line low for a long duration (at least 480 µs).
  2. Master Release: The master releases the line, and the pull-up resistor brings it high.
  3. Slave Presence Pulse: After detecting the rising edge, any slave device on the bus will wait 15-60 µs and then pull the line low for 60-240 µs to signal its presence.

The master must detect this low pulse from the slave to confirm a device is connected before proceeding.

The master initiates all communication with a reset pulse.

Write and Read Time Slots

After a successful reset, all data is transferred bit-by-bit within strictly-timed "slots," each lasting approximately 60-120 µs. The master always initiates every time slot by pulling the DQ line low.

Write '1' Slot

To write a logic '1', the master pulls the line low for a **very short time** (1-15 µs) and then releases it. The pull-up resistor keeps the line high for the rest of the slot.

Write '0' Slot

To write a logic '0', the master pulls the line low for the **entire duration** of the time slot (at least 60 µs) to ensure the slave device registers a zero.

Read Slot

To read a bit, the master also starts by pulling the line low for a short time (1-15 µs) and then releases it. It must then quickly switch its GPIO to input mode and sample the line's state. If a slave wants to send a '0', it will pull the line low. If it wants to send a '1', it will do nothing, allowing the line to remain high. The master must read the line **within 15 µs** of the start of the slot.

Example — Reading a DS18B20 Temperature

A practical transaction involves multiple steps. To read the temperature from a DS18B20 sensor, a typical sequence is:

  1. Reset/Presence: The master initiates the sequence and checks for the sensor.
  2. Master Writes 0xCC: This is the "Skip ROM" command, which addresses all devices on the bus.
  3. Master Writes 0x44: This is the "Convert T" command, which tells the sensor to start a temperature measurement. This can take up to 750ms.
  4. Master Polls: The master performs "Read Slots" repeatedly. The sensor will respond with a '0' while it is busy and a '1' when the conversion is complete.
  5. Reset/Presence: A new transaction is started.
  6. Master Writes 0xCC and 0xBE: Skip ROM again, followed by "Read Scratchpad," which prepares the sensor to transmit its data.
  7. Master Reads Data: The master performs 16 consecutive "Read Slots" to receive the 2-byte temperature reading from the sensor.

Best Practices & Troubleshooting

  • Precise Delays: Firmware implementations must use a precise microsecond delay routine or a timer-based state machine. Standard software delays are often too unreliable due to compiler optimizations or interrupt latency.
  • Pull-up Resistor Value: A 4.7kΩ resistor is standard, but for long cables or multiple devices, a lower value (e.g., 2.2kΩ) may be needed to ensure fast rise times.
  • Verify with an Oscilloscope: The best way to debug 1-Wire issues is to observe the signals on an oscilloscope. This immediately reveals timing problems that are difficult to find in code.
  • Parasite Power: If devices are using parasite power (drawing power from the data line), the master must provide a strong pull-up (e.g., using a MOSFET) immediately after commands that require significant power, like the `0x44` (Convert T) command.

Conclusion

The 1-Wire protocol offers a hardware-efficient interface but demands strict, software-driven timing. Its reliability depends entirely on adhering to the microsecond-level specifications for reset, presence, and bit-level communication. Visualizing these interactions with timing diagrams is an invaluable step in developing robust firmware for any 1-Wire application.