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I²C Communication Protocol Explained: Addressing, Timing, and Design

How the Inter-Integrated Circuit (I²C) bus works: its operation, configurations, and critical design aspects for reliable communication.

Erratum
Updated
  • Before this date the guide said that master and slave drive SDA "simultaneously" only for START/STOP. START and STOP are generated by the master alone; simultaneous driving happens during multi-master arbitration.
  • The layout section advised keeping SDA and SCL close together. UM10204 §7.5 recommends separating them with VDD/VSS on longer runs to limit crosstalk. The 400 pF limit, the pull-up formulas and the bus-clear procedure are now taken from the specification. The timing diagrams were redrawn so SDA changes only while SCL is low and the STOP condition is shown.

Sources: NXP UM10204 Rev. 7.0 (§3.1.16 Bus clear, §7.1 Pull-up sizing, §7.5 Wiring pattern).

The Inter-Integrated Circuit (I²C or I2C) bus is a synchronous, multi-master, multi-slave, packet-switched, single-ended, serial computer bus invented in 1982 by Philips Semiconductor (now NXP Semiconductors). It is widely used for attaching lower-speed peripheral ICs to processors and microcontrollers in short-distance, intra-board communication.

This guide explores the fundamentals of I²C, including its core signals, data transfer mechanism with START/STOP conditions, addressing, acknowledgments (ACK/NACK), various speed modes, and essential PCB layout considerations, including the critical role of pull-up resistors.

Core I²C Signals (The "2-Wire" Interface)

A standard I²C connection involves only two bidirectional lines, plus power and ground. This simplicity is a key advantage. Both lines require pull-up resistors to the positive supply voltage.

Standard I²C Bus (1 Master ↔ 1 Slave) VCC Rp Rp SCL SDA MASTER (e.g. MCU) SLAVE (e.g. Sensor)
Typical two‑wire I²C connection with pull‑up resistors (Rp).

1. SCL (Serial Clock)

  • Function: Provides the clock signal that synchronizes data transfer. Generated by the I²C Master.
  • Direction: Driven by the Master. Slaves can, however, hold SCL low to pause communication (clock stretching).
  • Characteristic: Requires an external pull-up resistor to VCC. The line is high when idle or when no device is pulling it low.

2. SDA (Serial Data)

  • Function: Carries the actual data between Master and Slave.
  • Direction: Bidirectional. The device that transmits pulls SDA low for 0 bits and releases it for 1 bits; the receiver pulls it low for ACK. START and STOP are generated by the master only. Because every output is open-drain, two masters can drive SDA at the same time during arbitration: a master that releases SDA (1) but sees it low knows it has lost.
  • Characteristic: Requires an external pull-up resistor to VCC. Data bits are transferred one at a time.

Fundamental I²C Operations

I²C communication is defined by several key conditions and signals:

START Condition (S)

A Master initiates a transaction by generating a START condition. This is defined as a HIGH-to-LOW transition on the SDA line while SCL is HIGH.

Timing diagram — START condition (S).

STOP Condition (P)

A Master terminates a transaction by generating a STOP condition. This is defined as a LOW-to-HIGH transition on the SDA line while SCL is HIGH.

Timing diagram — STOP condition (P).

Repeated START Condition (Sr)

A Master can issue another START condition without first issuing a STOP condition. This is useful for changing communication direction (e.g., from write to read) with the same slave or addressing a new slave without relinquishing control of the bus.

Data Validity & Transfer

Data on SDA must be stable during the HIGH period of SCL. SDA can only change when SCL is LOW. One bit is transferred per SCL pulse. Every byte is transferred MSB (Most Significant Bit) first.

Addressing (7-bit and R/W)

After a START condition, the Master sends a 7-bit slave address followed by an 8th bit, the Read/Write (R/W) bit.

  • R/W = 0: Master intends to WRITE data to the Slave.
  • R/W = 1: Master intends to READ data from the Slave.

10-bit addressing also exists but is less common.

Acknowledgment (ACK) and Not Acknowledgment (NACK)

Every 8 bits (address byte or data byte) transferred must be acknowledged by the receiver. The transmitter releases the SDA line during the 9th clock pulse. The receiver then pulls SDA LOW for ACK, or leaves it HIGH for NACK.

  • ACK: Receiver successfully received the byte and is ready for more (or has provided data).
  • NACK by Slave: Slave cannot accept data (e.g., busy) or does not recognize the address/command.
  • NACK by Master (during read): Master signals to the slave that it has received the last byte and will issue a STOP or Repeated START next.

I²C Data Transfer Example: Writing Data

A typical I²C write transaction involves the master sending a 7‑bit address and write bit, followed by one or more data bytes, each acknowledged (ACK) by the slave.

Simplified timing for an I²C write transaction (A6–A0 = address bits, W = write bit, D7–D0 = data bits).

I²C Data Transfer Example: Reading Data

A typical I²C read transaction begins with the master addressing the slave for reading. The master then provides clock pulses while the slave places data on SDA. The master ACKs every byte except the final one, where it sends a NACK to signal the end of the read, followed by a STOP.

Simplified timing for an I²C read transaction (A6–A0 = address bits, R = read bit, D7–D0 = data bits).

The Importance of Pull‑Up Resistors

I²C devices use open‑drain (or open‑collector) outputs on SDA and SCL: they can pull the line LOW but cannot drive it HIGH. External pull‑up resistors are therefore essential to …

  • Restore the line to a HIGH (idle) level whenever no device is pulling it LOW.
  • Let multiple devices share the bus with a wired‑AND configuration—if any device pulls LOW, the entire line goes LOW.

The value of the pull‑up resistor (Rp) is a trade‑off:

  • Rp too high → slow rise‑times caused by bus capacitance, limiting maximum speed; the line may fail to reach the required VIH.
  • Rp too low → higher current every time the line is pulled LOW; the sink current might exceed a device’s IOL capability, preventing it from achieving a valid VOL.

UM10204 gives the window directly: Rp(min) = (VDD − VOL(max)) / IOL and Rp(max) = tr / (0.8473 · Cb), with VOL = 0.4 V at IOL = 3 mA for Standard/Fast-mode devices, and tr = 1000 ns (100 kHz) or 300 ns (400 kHz). Example: 3.3 V, 100 pF, 400 kHz → Rp(min) ≈ 0.97 kΩ and Rp(max) ≈ 3.5 kΩ, so the common 4.7 kΩ is too weak there, while it is fine at 100 kHz. The I²C pull-up planner does this calculation for your bus.

Clock Stretching

A slave can keep the SCL line LOW after it receives (or sends) a bit if it needs more time —this is clock stretching. The master must detect the LOW level, wait until the slave releases SCL, and then continue.

Slave holds SCL LOW to stretch the clock.

I²C Bus Speeds

I²C supports several speed modes:

  • Standard Mode (Sm): Up to 100 kbit/s.
  • Fast Mode (Fm): Up to 400 kbit/s.
  • Fast Mode Plus (Fm+): Up to 1 Mbit/s. Requires more powerful output drivers.
  • High-Speed Mode (Hs-mode): Up to 3.4 Mbit/s. Involves a high-speed master code sent in Fm, then switching to faster Hs-mode timing.
  • Ultra Fast-mode (UFm): Up to 5 Mbit/s. Unidirectional, push-pull (no pull-ups typically during UFm data transfer). Less common.

The actual speed achievable depends on pull-up resistor values, bus capacitance, and device capabilities.

Advantages of I²C

  • Only two wires needed: SCL and SDA (plus power/ground), saving MCU pins.
  • Built-in addressing: Each device has a unique address, allowing many devices on the same bus.
  • Acknowledgment mechanism: Confirms successful byte transfer (ACK/NACK).
  • Multi-master capability: More than one master can exist on the bus (requires arbitration logic).
  • Well-defined standard: Widely adopted and understood.
  • Board-level and short cable runs: within the capacitance budget, a bus can leave the board on a short cable (see the 1 m wiring workflow).

Disadvantages of I²C

  • Slower than SPI: Generally lower maximum data rates.
  • Complexity: Protocol is more complex than SPI due to addressing, ACK/NACK, START/STOP.
  • Pull-up resistors required: Adds to component count and power consumption (when lines are low).
  • Bus capacitance limit: Total capacitance on SDA and SCL limits the number of devices and the bus length. UM10204 specifies 400 pF per line for Standard- and Fast-mode and 550 pF for Fast-mode Plus.
  • Open-drain outputs: Can lead to slower signal rise times compared to push-pull outputs.
  • Address collisions: Possible if devices have hardcoded or limited configurable addresses.

PCB Layout & Routing Best Practices for I²C

Good PCB layout is crucial for reliable I²C, especially at higher speeds (Fm, Fm+, Hs-mode):

  • Short Traces: Keep SCL and SDA traces as short as possible to minimize bus capacitance and signal delay.
  • One set of pull-ups per bus: pull-ups on several boards end up in parallel; check that the combined value stays above Rp(min). Placing them near the master is the usual choice.
  • Minimize capacitance: every device pin, connector and ESD diode adds a few pF; count them in Cb.
  • Grounding: Use a solid ground plane for a stable reference. Ensure all devices have good, low-impedance ground connections.
  • Separate SDA from SCL: the lines are most sensitive to crosstalk when high (only the pull-up holds them). For runs longer than about 10 cm without a ground plane, UM10204 §7.5 recommends the order SDA – VDD – VSS – SCL (or SDA – VSS – SCL), and in twisted-pair cable each line twisted with its own VSS return. Keep both away from switching nodes.
  • Rise time first: at 100–400 kHz, stubs and trace impedance matter much less than total capacitance and pull-up strength; at Fast-mode Plus and above, check edges with a scope.

Common Pitfalls & Debugging I²C

I²C can be tricky to get working correctly:

  • Missing or Incorrect Pull-Up Resistors: The #1 problem. SCL/SDA lines float or don't reach valid HIGH levels. Values might be too high (slow rise times) or too low (VOL not met).
  • Incorrect Slave Address: Ensure the 7-bit address used by the master matches the slave's actual address. Remember that addresses are often specified as 7-bit, but the first byte sent on the bus is (7-bit address << 1) | R/W_bit.
  • ACK/NACK Issues: Master not checking for ACK, or slave not ACKing correctly. Master not NACKing the last byte of a read.
  • START/STOP/Repeated START Condition Violations: Incorrect timing or signal transitions for these conditions.
  • Timing Issues: Clock speed too high for a particular slave or for the bus capacitance. Setup/hold time violations.
  • Bus Contention: Multiple devices trying to drive SDA at the same time inappropriately (e.g., two masters without proper arbitration, or a slave fault).
  • Noise: Glitches on SCL or SDA can corrupt data or be misinterpreted as START/STOP.
  • Unpowered devices clamping the bus: a device without supply can pull SDA/SCL towards its VDD through its ESD diodes (and be back-powered). Use devices specified as "I/O fail-safe" or isolate them with a buffer.
  • Bus stuck low: if a slave was reset in the middle of a read it can hold SDA low. UM10204 §3.1.16: the master sends nine SCL pulses so the slave finishes its byte and releases SDA, then issues a STOP; if SCL itself is stuck low, use a hardware reset or a power cycle.
  • Debugging tip: a logic analyzer decodes addresses and ACKs; an oscilloscope shows whether the rise time and low level are within spec. You usually need both.

Conclusion

The I²C bus is a powerful and widely adopted two-wire interface ideal for short-distance communication with a multitude of peripheral devices. Its pin-saving design, addressing scheme, and acknowledgment system make it a robust choice for many embedded applications.

While simpler in terms of pin count than SPI, the I²C protocol has its own complexities, particularly regarding addressing, ACK/NACK handling, and the critical role of pull-up resistors and bus capacitance. Careful attention to device datasheets, proper PCB layout, and thorough debugging are key to successful I²C implementation.

Troubleshooting I²C?

Size the pull-ups for your real bus capacitance, then follow the wiring checklist for cables.

Open the I²C pull-up planner

References & Further Reading

See Also