Design + audit + worst-case corners

Buck / Boost Designer (Inductor + Caps + Audit)

Q: What ripple current target should I use for the inductor?

A common starting point is 20–40% ripple. For a buck, the tool defines ripple as ΔIL/Iout(max). For a boost, ripple is referenced to the average inductor (input) current at the worst-case corner. Use tighter ripple when you care about output ripple/EMI, and higher ripple when you want smaller inductors and accept higher peak currents.

First-pass sizing for buck and boost converters: pick ripple targets, get L/C starting points, sanity-check a chosen BOM, explore worst-case corners, and export a review-ready summary.

Quick start (1 minute)

Pick Buck or Boost, then enter Vin range, Vout, and Iout range.
In Design mode, pick a ripple target and an output ripple limit; the tool gives L/C starting values and ripple currents.
In Audit mode, paste your chosen L/C ratings; the tool checks worst-case corners and highlights margins and risks.

Always validate against your regulator datasheet (limits + stability), and treat layout as part of the design (hot loop, return paths, probing).

This tool has two workflows: Design (compute L/C starting points) and Audit (validate a chosen BOM at worst-case corners).

Mode

Buck assumptions: CCM first-order sizing. Ripple ratio is referenced to Iout(max).

Topology sketch + intuition

Vin is pulsed at the switch node; L + Cout filter it into a DC output.
In CCM, the inductor current is roughly triangular around Iout.
Real regulators add non-idealities (Rds(on), diode drop, min on/off time, etc.).

Inputs

All fields clamp to sane ranges.

Operating point

Vin (min)

Vin (max)

Vout

Switching frequency (kHz)

Iout (min)

Iout (max)

Targets & assumptions

Inductor ripple target (%)

Vout ripple target (mVpp)

Cout effective ESR (mΩ)

Cout effective factor (%)

Sensitivity view

Results

Worst-case corner + quick sanity checks.

Design corner

---

Duty: ---

Inductor (Lmin / ΔIL)

---

ΔIL: ---

Peak current (Ipk)

---

CCM boundary: ---

Cout (min)

---

No-ESR: ---

Predicted ripple (worst)

---

Ivalley: ---

RMS currents

Cout Irms: ---

Cin Irms: ---

Inductor current waveform

Ipk @ Iout(max): ---

Ivalley @ Iout(min): ---

ΔIL (pp): ---

Duty: ---

Blue: Iout(max). Gray: Iout(min). Mode: ---

Audit notes

Inductor copper loss estimate: ---

Inductor ΔT estimate: ---

Notes: copper-only (DCR). Excludes AC winding loss and core loss (which can dominate at high fSW).

Isat margin: ---

Worst-case corner explorer

Vin	Iout	Duty	ΔIL	Ipk	Ivalley	Vout ripple

Corners use the recommended L/C in Design mode, or your chosen parts in Audit mode.

Sensitivity (what moves the needle)

Generated checklist (review-ready)

Scope plan (what to measure)

Frictionless handoff

Share & export

Copy a link, paste a Markdown summary, or export a CSV/PDF for reviews.

References: common CCM sizing relationships used across vendor app notes; validate against your controller/regulator datasheet limits and test on hardware.

Frequently asked questions

Is this a full buck/boost converter design tool?

No. This is a first-pass sizing and audit tool: it estimates L/C, ripple currents, and worst-case corners using common CCM approximations. You still need the regulator datasheet (limits, compensation/stability, min on/off time, and layout guidance) for a complete design.

What ripple current target should I use for the inductor?

A common starting point is 20–40% ripple. For a buck, this tool defines ripple as ΔIL/Iout(max). For a boost, ripple is referenced to the average inductor (input) current at the worst-case corner. Use tighter ripple when you care about output ripple/EMI, and higher ripple when you want smaller inductors and accept higher peak currents.

Why does measured output ripple differ from the estimate?

Output ripple depends heavily on effective capacitance (DC bias derating), ESR/ESL, PCB loop inductance, control mode (PFM/skip at light load), and measurement technique. Use a spring ground and bandwidth limiting when measuring ripple, and treat the estimate as an order-of-magnitude check.

How much margin should I keep for inductor saturation?

Avoid running at the saturation knee. As a practical baseline, target Isat ≥ 1.2× to 1.5× Ipeak at worst-case conditions, and confirm the datasheet definition of Isat (drop in inductance vs current) and temperature derating.

Do I need to stay in CCM at light load?

Not necessarily. Many modern regulators enter discontinuous conduction (DCM), pulse-skipping, or PFM at light load to improve efficiency. What matters is that your regulator supports the intended mode and that ripple/EMI are acceptable in those conditions.