What this solves
It removes the annoying part of debug bring-up: matching the target header to the probe connector without swapping SWDIO, SWCLK, VTref, or reset.
Compare common target headers and probes, highlight matching pins, and generate a wiring table before you plug anything in.
These presets set the connector, probe, filter, and reset preference in one click.
It removes the annoying part of debug bring-up: matching the target header to the probe connector without swapping SWDIO, SWCLK, VTref, or reset.
For Cortex-M boards, start with SWD plus nRESET. Keep VTref as a
sensed voltage reference, not as a power rail.
Use the JTAG filter for older ARM systems, FPGAs, boundary-scan tasks, or any target that
genuinely needs TDI, TDO, and nTRST.
Pick a target header and probe, then narrow the view to SWD or JTAG if needed.
Quick static reference for the headers that show up most often in practice.
| Header | Typical use | Core pins | Notes |
|---|---|---|---|
| ARM 10-pin / Cortex | Modern Cortex-M SWD or compact JTAG | VTref, SWDIO/TMS, SWCLK/TCK, GND, nRESET | Small, common, and usually the best default. |
| ARM 20-pin | Legacy ARM, full JTAG, some FPGA workflows | VTref, TMS, TCK, TDI, TDO, nTRST, nRESET | Bulky but explicit. Watch optional +5 V on pin 19. |
| STDC14 | ST-Link V3 and STM32 ecosystems | ARM10 core plus optional VCP pins | Pins 13 and 14 often carry probe UART. |
| Tag-Connect TC2050 | Compact production or dense bring-up fixtures | Cortex-10 style signal set | No populated header on the PCB. |
| SWD 6-pin | Minimal SWD-only boards | VTref, SWDIO, SWCLK, GND, nRESET | Simple, but less flexible than Cortex-10. |
Select ARM 10-pin Cortex Debug as the target and ST-Link/V2 as the probe. Use the Minimal SWD filter to keep the essentials on screen: SWDIO, SWCLK, GND, VTref, with nRESET recommended.
Choose ARM 20-pin Standard JTAG as the target and Segger J-Link (20-pin) as the debugger. The table will expose TMS, TCK, TDI, TDO, nTRST, nRESET, and the rest of the connector.
Pick a Cortex-style target connector such as MIPI-10 or TC2050 and choose Raspberry Pi Pico (Picoprobe). Common defaults are GP2=SWCLK and GP3=SWDIO, with GP4/GP5 often used for UART.
Note on MIPI-10: in many documents this effectively refers to the same practical wiring family as the Cortex Debug 10-pin header. This tool treats them as equivalent.
JTAG usually needs 4 to 5 active signals: TMS, TCK, TDI, TDO, and sometimes nTRST. SWD reduces that to SWDIO and SWCLK, which is why it is the common Cortex-M default.
VTref is a probe input: it tells the probe the target I/O level. Do not power the target through VTref. On ARM-20, pin 19 can expose a separate +5 V output on some probes, so treat that pin carefully.
No. VTref is usually a probe input used to sense the target I/O voltage. It should normally not be used to power the target.
Start with SWD unless the target specifically requires JTAG features. It uses fewer pins and is the common default for Cortex-M bring-up.
Not always, but it is strongly recommended. The core set is usually SWDIO,
SWCLK, GND, and VTref, while nRESET
improves recovery when firmware or low-power states block debug attach.
In practice they usually refer to the same 10-pin Cortex Debug connector family. This tool treats them as equivalent for wiring purposes.
Find debugger VID/PID combos while diagnosing boards.
Flash (DAPLink), read memory, and run SWD link checks from the browser.
Capture boot logs and run quick tests while validating SWD/JTAG wiring.
Deepen your understanding of TAP states and debug chains.