Via Stitching Calculator (IPC-2221A + EMI)
Calculate optimal via stitching pattern for ground planes. Get EMI-compliant spacing (λ/20 rule) and via count based on IPC-2221A standards.
⚙️ Zone Parameters
Width of the copper zone
Height of the copper zone
Signal Type
Via Specifications
📊 Results
Total Vias Needed
---
--- × --- grid pattern
Recommended Spacing
---
EMI (λ/20): --- | IPC: ---
Parallel Resistance
---
Coverage
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📐 Grid Preview
How It Works
EMI λ/20 Rule
For EMI reduction, via spacing should not exceed λ/20 (one-twentieth of the signal wavelength):
λ = c / f_max (wavelength)
spacing_max = λ / 20 (EMI rule)
This prevents ground plane resonances and reduces radiated emissions by over 40%.
IPC-2221A Spacing
IPC-2221A recommends minimum via-to-via spacing based on:
- Manufacturing capabilities (typically 0.5mm minimum)
- Voltage clearance requirements
- Thermal management considerations
Via Count Calculation
spacing = max(λ/20, IPC_min)
vias_x = floor(width / spacing) + 1
vias_y = floor(height / spacing) + 1
total_vias = vias_x × vias_y
💡 Design Tip: Place vias strategically near IC power pins and noise sources. For high-speed designs (>100 MHz), consider tighter spacing than calculated minimum.
Frequently Asked Questions
What is via stitching and why is it important?
Via stitching connects ground (or power) planes on different PCB layers using an array of vias. This reduces ground bounce, improves signal return paths, and minimizes EMI by providing low-impedance connections between layers.
How does the λ/20 rule work?
The λ/20 rule states that via spacing should not exceed one-twentieth of the signal wavelength. This prevents the ground plane from resonating at the signal frequency. For a 1 GHz signal, λ = 30cm, so spacing should be ≤15mm.
Can I use this calculator with KiCad?
Yes! Use the calculated spacing to manually place vias in KiCad. Our upcoming KiCad plugin will automate via stitching with collision detection and preview.
What spacing should I use for DC power planes?
For pure DC (static signals), EMI is not a concern. Use IPC minimum spacing (typically 0.5-1mm) and place vias based on current distribution needs. Focus on strategic placement near power pins rather than uniform grid.