Via Stitching Calculator (IPC-2221A + EMI)
Estimate a via stitching grid for ground or shield copper, compare the IPC manufacturing minimum against the lambda over 20 EMI spacing limit, and see whether the geometry is comfortable, constrained, or in conflict.
Quick start examples
This tool is best for first-pass spacing logic. Final stitching is usually driven by edges, seams, return paths, connectors, and noise sources, not only by a uniform fill grid.
Inputs
Zone geometry, frequency context, and via assumptions.
Via geometry
Values also auto-update while you edit them.
Spacing check
Recommended spacing
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Run the calculation to see whether the chosen geometry is comfortable, EMI-limited, or in direct conflict with fabrication spacing.
Grid
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EMI max spacing
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IPC minimum
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Parallel resistance
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Coverage
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Actual spacing
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Frequency assumption
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Grid preview
Scaled view of the current grid estimate across the requested zone.
Compliance
Warnings and guidelines
No warnings yet.
Layout guidance
Save the stitching assumption
Useful when you want to capture a spacing decision in notes, reviews, or design handoff docs.
How to read the result
Two constraints, opposite directions
IPC-style spacing is a minimum fabrication or clearance limit, while the EMI lambda over 20 rule is a maximum spacing target. A workable design needs spacing that stays above the minimum and below the maximum.
Why conflicts happen
At higher frequencies, the EMI maximum gets smaller. At some point it can fall below your realistic minimum spacing, especially with coarse via geometry or edge clearances. That is a real engineering tradeoff, not just a calculator problem.
Practical rule: for many boards, start by stitching edges, seams, connectors, noisy IC boundaries, and return path discontinuities first. A mathematically uniform full-area grid is rarely the only or the best answer.
Frequently asked questions
What is the lambda over 20 rule?
It is a maximum spacing guideline used to keep stitched reference copper electrically tight enough at a given frequency so the return structure does not become too sparse for EMI control.
What if IPC minimum spacing conflicts with the EMI target?
Then you cannot satisfy both with the chosen geometry. Usually you either accept the compromise, change the via assumptions, or stitch only the areas that matter most instead of forcing a uniform grid.
Do I always want the densest grid possible?
No. Dense stitching can hurt routing and often adds little value away from edges, seams, layer transitions, or noisy regions. Use density intentionally.