I²C Communication Protocol Explained: Addressing, Timing, and Design

The Inter-Integrated Circuit (I²C or I2C) bus is a synchronous, multi-master, multi-slave, packet-switched, single-ended, serial computer bus invented in 1982 by Philips Semiconductor (now NXP Semiconductors). It is widely used for attaching lower-speed peripheral ICs to processors and microcontrollers in short-distance, intra-board communication.

This guide explores the fundamentals of I²C, including its core signals, data transfer mechanism with START/STOP conditions, addressing, acknowledgments (ACK/NACK), various speed modes, and essential PCB layout considerations, including the critical role of pull-up resistors.

Core I²C Signals (The "2-Wire" Interface)

A standard I²C connection involves only two bidirectional lines, plus power and ground. This simplicity is a key advantage. Both lines require pull-up resistors to the positive supply voltage.

Fundamental I²C Operations

I²C communication is defined by several key conditions and signals:

I²C Data Transfer Example: Writing Data

A typical I²C write transaction involves the master sending a 7‑bit address and write bit, followed by one or more data bytes, each acknowledged (ACK) by the slave.

I²C Data Transfer Example: Reading Data

A typical I²C read transaction begins with the master addressing the slave for reading. The master then provides clock pulses while the slave places data on SDA. The master ACKs every byte except the final one, where it sends a NACK to signal the end of the read, followed by a STOP.

The Importance of Pull‑Up Resistors

I²C devices use open‑drain (or open‑collector) outputs on SDA and SCL: they can pull the line LOW but cannot drive it HIGH. External pull‑up resistors are therefore essential to …

• Restore the line to a HIGH (idle) level whenever no device is pulling it LOW.
• Let multiple devices share the bus with a wired‑AND configuration—if any device pulls LOW, the entire line goes LOW.

The value of the pull‑up resistor (R_p) is a trade‑off:

• R_p too high → slow rise‑times caused by bus capacitance, limiting maximum speed; the line may fail to reach the required VIH.
• R_p too low → higher current every time the line is pulled LOW; the sink current might exceed a device’s IOL capability, preventing it from achieving a valid VOL.

Typical values range from 1 kΩ to 10 kΩ, depending on bus speed, voltage, and capacitance. A common compromise is 4.7 kΩ for 100 kHz or 400 kHz buses at 3.3 V / 5 V with moderate capacitance, but always confirm with the device datasheets and total bus capacitance.

Clock Stretching

A slave can keep the SCL line LOW after it receives (or sends) a bit if it needs more time —this is clock stretching. The master must detect the LOW level, wait until the slave releases SCL, and then continue.

I²C Bus Speeds

I²C supports several speed modes:

• Standard Mode (Sm): Up to 100 kbit/s.
• Fast Mode (Fm): Up to 400 kbit/s.
• Fast Mode Plus (Fm+): Up to 1 Mbit/s. Requires more powerful output drivers.
• High-Speed Mode (Hs-mode): Up to 3.4 Mbit/s. Involves a high-speed master code sent in Fm, then switching to faster Hs-mode timing.
• Ultra Fast-mode (UFm): Up to 5 Mbit/s. Unidirectional, push-pull (no pull-ups typically during UFm data transfer). Less common.

The actual speed achievable depends on pull-up resistor values, bus capacitance, and device capabilities.

Advantages of I²C

• Only two wires needed: SCL and SDA (plus power/ground), saving MCU pins.
• Built-in addressing: Each device has a unique address, allowing many devices on the same bus.
• Acknowledgment mechanism: Confirms successful byte transfer (ACK/NACK).
• Multi-master capability: More than one master can exist on the bus (requires arbitration logic).
• Well-defined standard: Widely adopted and understood.
• Moderate distances possible: Compared to very short-range interfaces.

Disadvantages of I²C

• Slower than SPI: Generally lower maximum data rates.
• Complexity: Protocol is more complex than SPI due to addressing, ACK/NACK, START/STOP.
• Pull-up resistors required: Adds to component count and power consumption (when lines are low).
• Bus capacitance limit: Total capacitance on SDA and SCL lines limits the number of devices and physical bus length, especially at higher speeds. Max specified is typically 400 pF for Sm/Fm.
• Open-drain outputs: Can lead to slower signal rise times compared to push-pull outputs.
• Address collisions: Possible if devices have hardcoded or limited configurable addresses.

PCB Layout & Routing Best Practices for I²C

Good PCB layout is crucial for reliable I²C, especially at higher speeds (Fm, Fm+, Hs-mode):

• Short Traces: Keep SCL and SDA traces as short as possible to minimize bus capacitance and signal delay.
• Pull-up Resistor Placement: Place pull-up resistors appropriately. Typically one set of pull-ups per bus. They can be grouped or placed near the master, or distributed if it helps. Ensure they are on the SCL and SDA lines.
• Minimize Capacitance: Route to avoid unnecessary vias and long parallel runs that increase capacitance. Choose low-capacitance components if possible.
• Grounding: Use a solid ground plane for a stable reference. Ensure all devices have good, low-impedance ground connections.
• Spacing: Keep SCL and SDA traces reasonably close together but maintain spacing from noisy signals (e.g., switch-mode power supplies, high-speed digital lines) to prevent crosstalk.
• Avoid Stubs: Minimize or eliminate stubs on SCL and SDA lines.
• Trace Width: Typical signal trace widths are usually fine, but ensure they can handle the current if pull-ups are very strong (though this is rare for I2C signal lines themselves).

Common Pitfalls & Debugging I²C

I²C can be tricky to get working correctly:

• Missing or Incorrect Pull-Up Resistors: The #1 problem. SCL/SDA lines float or don't reach valid HIGH levels. Values might be too high (slow rise times) or too low (VOL not met).
• Incorrect Slave Address: Ensure the 7-bit address used by the master matches the slave's actual address. Remember that addresses are often specified as 7-bit, but the first byte sent on the bus is (7-bit address << 1) | R/W_bit.
• ACK/NACK Issues: Master not checking for ACK, or slave not ACKing correctly. Master not NACKing the last byte of a read.
• START/STOP/Repeated START Condition Violations: Incorrect timing or signal transitions for these conditions.
• Timing Issues: Clock speed too high for a particular slave or for the bus capacitance. Setup/hold time violations.
• Bus Contention: Multiple devices trying to drive SDA at the same time inappropriately (e.g., two masters without proper arbitration, or a slave fault).
• Noise: Glitches on SCL or SDA can corrupt data or be misinterpreted as START/STOP.
• Floating Lines (if slave unpowered): If a slave device is unpowered but connected to the bus, its protection diodes can clamp the lines.
• Debugging Tip: A logic analyzer or oscilloscope with I²C protocol decoding is invaluable for observing signals, addresses, data, and ACKs.

Conclusion

The I²C bus is a powerful and widely adopted two-wire interface ideal for short-distance communication with a multitude of peripheral devices. Its pin-saving design, addressing scheme, and acknowledgment system make it a robust choice for many embedded applications.

While simpler in terms of pin count than SPI, the I²C protocol has its own complexities, particularly regarding addressing, ACK/NACK handling, and the critical role of pull-up resistors and bus capacitance. Careful attention to device datasheets, proper PCB layout, and thorough debugging are key to successful I²C implementation.

References & Further Reading

• NXP (formerly Philips) I²C-bus specification and user manual (UM10204).
• Datasheets for specific MCUs and I²C peripheral devices.
• Application notes from semiconductor manufacturers on I²C implementation, pull-up resistor calculation, and bus loading.