Microstrip Impedance Calculator: 50 Ohm PCB Trace Width
Estimate single-ended PCB microstrip impedance from geometry, or solve the trace width for a target impedance. Add your fabrication width tolerance to see the likely impedance window before asking the board house for final sign-off.
Quick start examples
Presets load plausible stackups so you can see how geometry drives Z0. Final numbers should come from your fabricator stackup and target impedance table.
Inputs
Geometry for a single-ended outer-layer microstrip.
Finished trace width after the fab process.
Distance from trace to its solid reference plane.
Heavy copper lowers impedance and matters more when H is small.
Use the actual laminate Dk from the stackup if you have it.
Use 50, 60, 75 ohm, or a stackup-specific single-ended target.
Enter the fab tolerance you want to evaluate; 0.025 mm is only an example.
What this assumes
- Single-ended microstrip over a continuous reference plane.
- Closed-form quasi-static estimate, not full-wave field solving.
- No mask-over correction, roughness, weave, or frequency dispersion modeling.
Primary estimate
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Thickness-corrected microstrip estimate for early routing decisions.
Selected target
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Effective Er
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W/H ratio
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Delay
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Approx. ps/mm
Cross-check
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Fabrication width window
Narrow edge: --
Wide edge: --
Enter your finished-width tolerance.
Interpretation
Cross-section view
Not to scaleThe calculator treats this as an outer-layer trace above a solid plane. Coplanar waveguide, solder mask, and differential coupling need separate models.
Best use
Early stackup exploration, routing-width sanity checks, and quick conversations with a PCB fabricator before formal impedance tables arrive.
Not enough for
Final sign-off of USB, PCIe, DDR, or RF-critical nets where solder mask, roughness, glass weave, dispersion, or differential coupling materially move the answer.
Most common mistake
Using a generic Er like 4.3 for final routing. Real FR-4 and prepreg systems vary with resin content and frequency, so the fabricator stackup usually wins.
Practical workflow
How to estimate a 50 ohm PCB trace width
- 1. Enter the real stackup. Use finished copper, trace-to-plane height, and laminate Dk from the fabricator.
- 2. Set 50 ohm and solve. The tool searches for the single-ended microstrip width that matches the selected model.
- 3. Add the fab tolerance. Review the impedance window, then send the target and layer definition to the board house for final compensation.
| Target | Typical use | Important limitation |
|---|---|---|
| 50 ohm | Common single-ended RF and transmission-line target | The width is stackup-specific, not a universal rule |
| 60 / 75 ohm | Vendor-specific single-ended nets and 75 ohm RF/video systems | Confirm the exact target in the interface or component documentation |
| USB / PCIe / Ethernet pairs | Coupled differential transmission lines | Do not divide the differential target by two and use this model; spacing and coupling need a differential solver |
Formula notes
Primary estimate
The main result uses a thickness-corrected closed-form microstrip estimate in the Hammerstad/Jensen family. It first adjusts the effective width, then computes effective dielectric constant and characteristic impedance.
u = W / H
Er_eff = (Er + 1)/2 + (Er - 1)/2 * f(u, Er)
Z0 = Z_air(u_eff) / sqrt(Er_eff)
This is a good engineering estimate for single-ended outer-layer routing, especially for comparing stackups and routing widths quickly.
Classical cross-check
The secondary value is a simpler classical wide-trace / narrow-trace closed-form estimate. Close agreement is reassuring. A larger gap means geometry or stackup details are making the answer more sensitive.
W' = W + thickness correction
Z0 ~= 60/sqrt(Er_eff) * ln(8H/W' + W'/(4H)) for narrow lines
Z0 ~= 120pi / (sqrt(Er_eff) * g(W'/H)) for wide lines
If your interface is critical, let the board house solve the final width from the actual laminate and etch compensation instead of chasing fractions of an ohm here.
Practical notes
What moves the answer the most
- Height to plane: increasing H raises impedance quickly.
- Trace width: increasing W lowers impedance.
- Copper thickness: heavier copper lowers impedance because the line behaves wider.
- Er: higher dielectric constant lowers impedance and slows propagation.
Before you freeze a width
- Ask whether the fabricator target assumes solder mask over the trace.
- Confirm the real laminate Dk at the relevant frequency, not a generic FR-4 value.
- Check minimum trace width and etch compensation if the line is narrow.
- Use the fab controlled-impedance coupon or TDR data for sign-off when the interface matters.
FAQ
How wide should a 50 ohm PCB trace be?
There is no universal width. The answer depends mainly on distance to the reference plane, laminate Dk, finished copper thickness, and fabrication process. Enter the real stackup, use Solve trace width for a first pass, then ask the fabricator to confirm the compensated finished width.
Which Er should I use for FR-4 in impedance calculations?
Use the laminate Dk from the fabricator stackup at the relevant frequency. If you do not have it yet, a first-pass value around 3.9 to 4.2 is reasonable, but final routing should use the actual laminate data.
Is this enough to sign off a 50 ohm interface?
No. This tool is useful for first-pass sizing and sanity checks. Final sign-off should use the board fabricator controlled-impedance stackup, etch compensation, and ideally field solver or TDR validation for critical interfaces.
How much does copper thickness matter?
It matters more as dielectric height gets smaller or copper gets heavier. Thicker copper lowers impedance because the trace behaves electrically wider than its nominal width.
Does solder mask change microstrip impedance?
Usually yes. Solder mask raises the effective dielectric loading and tends to lower impedance by a few ohms, depending on stackup and geometry. Ask the fabricator whether the target assumes mask over the trace.