Thermal Vias & Copper Spreading (PCB Heat Transfer Guide + Estimator)

Thermal vias are simple to draw and surprisingly easy to get wrong. The core idea is: a via only helps if the copper on the other side can spread and dump the heat. This page focuses on practical layout decisions and a lightweight estimator you can use early in the PCB phase.

What thermal vias do (and what they do not)

A thermal via is simply a plated hole used as a heat conduit between copper layers (for example from a QFN exposed pad to a large internal/bottom ground plane). Compared to FR-4, copper conducts heat extremely well, so even a few vias can reduce through-board thermal resistance.

• Thermal vias: move heat between layers (thermal problem).
• Stitching vias: provide return paths / reduce loop area (EMI & signal integrity problem).
• Same geometry, different intent: you can place vias for both reasons, but the metrics are different.

Copper spreading (why planes matter)

Think of a thermal via array as a vertical heat pipe. If the plane it connects to is small (or thermally isolated), the via array quickly stops being the bottleneck. Spreading resistance in the copper pours/planes becomes the limiter.

• Area helps with diminishing returns: doubling plane size does not halve temperature rise forever (spreading follows a log-like law in simple models).
• Thickness helps linearly: 2 oz copper spreads roughly twice as well as 1 oz for the same geometry (for conduction in the copper).
• Heat needs an exit: exposed copper, airflow, a metal enclosure, thermal pads, or a heatsink are what ultimately set equilibrium.

Thermal via + copper spreading estimator

This estimator is best used as a sanity check (order of magnitude), not as a sign-off method. It models steady-state conduction only through the board and along copper. Real boards also depend on convection, radiation, and contact to the environment.

Layout patterns (practical)

QFN / DFN exposed pad

• Start from the package datasheet land pattern (thermal pad size, paste pattern, and via suggestions).
• Place an array of small vias inside the exposed pad to connect to a large plane (internal and/or bottom).
• If vias are inside the pad: plan for tenting, plugging, or via-in-pad filled/planarized to avoid solder wicking.
• Use larger copper on layers that can actually dump heat (exposed copper, airflow, enclosure contact).

Power MOSFET / drivers (hot switching parts)

• Separate the electrical loop (small, low inductance) from the thermal spreading area (big copper, many vias).
• Use a solid copper region under the drain pad/thermal pad to spread heat, then stitch into planes with thermal vias.
• Avoid letting thermal copper become a noisy antenna: keep switching nodes compact and well referenced.

LEDs and linear regulators (steady heat)

• If the board touches metal (enclosure/heatsink), route heat towards those contact points (copper pours + via arrays).
• Expose copper on an outside layer (no solder mask) if allowed to improve convection and enable thermal pad contact.
• Validate early with a thermocouple or IR camera—thermal surprises are cheap to fix before you spin.

Manufacturing & assembly notes

• Open vias in pads: can wick solder during reflow (voids, poor joint). Mitigate with tenting, plugging, or via-in-pad filled/planarized.
• Via-in-pad (VIPPO): improves assembly for fine pitch but has cost/lead-time implications. Use it when you need it.
• Thermal relief spokes: help solderability but reduce heat flow. Decide per pad: pins often use relief, thermal pads often want solid copper.
• Internal planes: if you have them, connect your thermal vias to those planes too (they add spreading volume).

Where the equations come from (and what is simplified)

The estimator uses steady-state conduction models. In its simplest form, conduction is:

• 1D conduction: R ≈ L / (k · A) where L is length, k thermal conductivity, and A cross-sectional area.
• Via barrel area: for a plated cylinder (shell) with inner radius r and plating thickness t, A ≈ π · ((r + t)² − r²).
• 2D radial spreading in a thin sheet: R ≈ ln(r2 / r1) / (2π · k · t) where t is copper thickness, and r1/r2 are equivalent radii.

Real PCBs are 3D, anisotropic, and exchange heat with air. Use this estimator to compare layouts and identify which block dominates (vias vs plane spreading), then validate with measurement or a proper thermal simulation if the margin is small.

References

• JEDEC JESD51 series — methodology for measuring and reporting package thermal metrics (θJA, θJC, θJB) on standardized boards.
• IPC-2221 — generic PCB design standard (useful for general via/geometry constraints, not a thermal sign-off document).
• Package datasheets / app notes — many IC vendors provide recommended exposed-pad and thermal-via patterns; treat them as the primary reference for a given package.

FAQ